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FINAL
AM29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V 10% for read and write operations -- Minimizes system level power requirements s Compatible with JEDEC-standards -- Pinout and software compatible with singlepower-supply Flash -- Superior inadvertent write protection s Package options -- 32-pin PLCC -- 32-pin TSOP -- 32-pin PDIP s Minimum 100,000 write/erase cycles guaranteed s High performance -- 55 ns maximum access time s Sector erase architecture -- Uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased. Also supports full chip erase. s Sector protection -- Hardware method that disables any combination of sectors from write or erase operations s Embedded Erase Algorithms -- Automatically preprograms and erases the chip or any combination of sectors s Embedded Program Algorithms -- Automatically programs and verifies data at specified address s Data Polling and Toggle Bit feature for detection of program or erase cycle completion s Erase suspend/resume -- Supports reading data from a sector not being erased s Low power consumption -- 20 mA typical active read current -- 30 mA typical program/erase current s Enhanced power management for standby mode -- <1 A typical standby current -- Standard access time from standby mode
GENERAL DESCRIPTION
The AM29F040 is a 4 Mbit, 5.0 Volt-only Flash memory organized as 512 Kbytes of 8 bits each. The AM29F040 is offered in a 32-pin package. This device is designed to be programmed in-system with the standard system 5.0 V V CC supply. A 12.0 V V PP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard AM29F040 offers access times between 55 ns and 150 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The AM29F040 is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 Volt Flash or EPROM devices. The AM29F040 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than one second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Publication# 17113 Rev: E Amendment/0 Issue Date: November 1996
Any individual sector is typically erased and verified in 1.0 seconds (if already completely preprogrammed). This device also features a sector erase architecture. The sector mode allows for 64K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The AM29F040 is erased when shipped from the factory. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 or by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. AMD's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The AM29F040 memory electrically erases the entire chip or all bits within a sector simultaneously via FowlerNordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s Eight 64 Kbyte sectors s Individual-sector, multiple-sector, or bulk-erase capability s Individual or multiple-sector protection is user definable
7FFFFh 6FFFFh 5FFFFh 64 Kbytes per Sector 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh 00000h
17113E-1
2
AM29F040
PRODUCT SELECTOR GUIDE
Family Part No: Ordering Part No: VCC = 5.0 V 5% VCC = 5.0 V 10% Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) 55 55 25 -55 -70 70 70 30 -90 90 90 35 -120 120 120 50 -150 150 150 55 AM29F040
BLOCK DIAGRAM
DQ0-DQ7 VCC VSS
Erase Voltage Generator
Input/Output Buffers
WE
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE OE
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A18
17113E-2
AM29F040
3
CONNECTION DIAGRAMS
PDIP A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC VCC A12 A15 A16 A18 A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
17113E-3 17113E-4
PLCC
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7
14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4
17113E-5
TSOP A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29F040 Standard Pinout OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29F040 Reverse Pinout 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
4
AM29F040
VSS
A17
WE
WE
PIN CONFIGURATION
A0-A18 = Address Inputs DQ0-DQ7 = Data Input/Output CE OE WE VSS VCC = Chip Enable = Output Enable = Write Enable = Device Ground = Device Power Supply (5.0 V 10% or 5%)
LOGIC SYMBOL
19 A0-A18 DQ0-DQ7 CE (E) OE (G) WE (W) 8
17113E-6
AM29F040
5
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM29F040 -55 E C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION AM29F040 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
Valid Combinations AM29F040-55 JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F040-70 AM29F040-90 AM29F040-120 AM29F040-150 PC, PCB, PI, PIB, PE, PEB, JC, JCB, JI, JIB, JE, JEB, EC, ECB, EI, EIB, EE, EEB, FC, FCB, FI, FIB, P11 FE, FEB
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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AM29F040
Table 1.
Operation Autoselect Manufacturer Code (Note 1) Autoselect Device Code (Note 1) Read (Note 4) Standby Output Disable Write Verify Sector Protect (Note 3) Autoselect Device Unprotect Code
AM29F040 User Bus Operations
CE L L L H L L L L OE L L L X H H L L WE H H H X H L H H A0 L H A0 X X A0 L H A1 L L A1 X X A1 H H A6 L L A6 X X A6 L L A9 VID VID A9 X X A9 VID VID I/O Code Code RD HIGH Z HIGH Z PD (Note 2) Code Code
Legend: L = Logic 0, H = Logic 1, X = Don't Care. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Tables 2 and 4. 2. Refer to Table 3 for valid PD (Program Data) during a write operation. 3. Refer to the section on Sector Protection. 4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
Read Mode
The AM29F040 has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time).
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6. The manufacturer and device codes may also be read via the command register, for instances when the AM29F040 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 4 (refer to Autoselect Command section). Byte 0 (A0 = VIL) represents the manufacturer's code (AMD = 01H) and byte 1 (A0 = VIH) the device identifier code (AM29F040 = A4H). All identifiers for manufacturer and device exhibit odd parity with the MSB (DQ7) defined as the parity bit. See Table 2.
Standby Mode
The AM29F040 has two standby modes, a CMOS standby mode (CE input held at VCC 0.5 V), when the current consumed is less than 5 A; and a TTL standby mode (CE is held at VIH) when the current required is reduced to approximately 1 mA. In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed.
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Table 2. AM29F040 Autoselect Codes
Type Manufacturer ID AM29F040 Device ID Sector Protection A18 X X A17 X X A16 X X A6 VIL VIL VIL A1 VIL VIL VIH A0 VIL VIH VIL Code (HEX) DQ7 01H A4H 01H* 0 1 0 DQ6 0 0 0 DQ5 0 1 0 DQ4 0 0 0 DQ3 0 0 0 DQ2 0 1 0 DQ1 0 0 0 DQ0 1 0 1
Sector Addresses
*Outputs 01H at protected sector addresses
Table 3.
A18 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 0 0 0 0 1 1 1 1
Sector Addresses
A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
Sector Protection
The AM29F040 features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 8). The sector protect feature is enabled using programming equipment at the user's site. The device is shipped with all sectors unprotected. Alternatively, AMD may program and protect sectors in the factory prior to shipping the device (AMD's ExpressFlashTM Service). It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A16, A17, and A18) are used to select the desired sector. The device produces a logical "1" at DQ0 for a protected sector and a logical "0" for an unprotected sector. See Table 2 for Autoselect codes.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/ Programming Waveforms for specific timing parameters.
Sector Unprotect
The AM29F040 also features a sector unprotect mode so that a protected sector may be unprotected to incorporate any changes in the code. The sector unprotect is enabled using programming equipment at the user's site.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0) and Erase Resume (30) commands are valid only while the Sector Erase operation is in progress. Either of the two reset commands will reset the device (when applicable).
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AM29F040
Table 4.
Bus Write Cycles Req'd 1 4 4 4 6 6 First Bus Write Cycle Addr XXXXH 5555H 5555H 5555H 5555H 5555H Data F0H
AM29F040 Command Definitions
Second Bus Write Cycle Addr Data Third Bus Write Cycle Addr Data Fourth Bus Read/Write Cycle Addr Data Fifth Bus Write Cycle Addr Data Sixth Bus Write Cycle Addr Data
Command Sequence Read/Reset Read/Reset Read/Reset Autoselect Byte Program Chip Erase Sector Erase
AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H
5555H 5555H 5555H 5555H 5555H
F0H 90H
RA 00H 01H
RD 01H A4H PD AAH AAH 2AAAH 55H 2AAAH 55H 5555H SA 10H 30H
A0H 80H 80H
PA 5555H 5555H
Sector Erase Suspend Sector Erase Resume
Erase can be suspended during sector erase with Addr (don't care), Data (B0H) Erase can be resumed after suspend with Addr (don't care), Data (30H)
Notes: 1. Address bits A15, A16, A17, and A18 = X = Don't Care for all address commands except for Program Address (PA), Sector Address (SA), Read Address (RA), and autoselect sector protect verify. 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector (see Table 3). 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 5. Read from non-erasing sectors is allowed in the Erase Suspend mode.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
The device contains a command autoselect operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from address XX01H returns the device code A4H (see Table 2). All manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Scanning the sector addresses (A16, A17, A18) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector. To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program setup command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The
AM29F040
9
rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to the read mode and addresses are no longer latched. Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may cause the device to exceed programming time limits (DQ5 = 1) or result in an apparent success, according to the data polling algorithm, but a read from reset/read mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 1 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "setup" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. A time-out of 80 s from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 80 s, otherwise that command will not be accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 80 s from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 80 s time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this period resets the device to read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (1 to 8). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 80 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to read mode. During the execution of the Sector Erase command, only the Erase Suspend and Erase Resume commands are allowed. All other commands will be ignored. Data polling must be performed at an address within any of the sectors being erased. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "setup" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The chip erase is performed sequentially one sector at a time. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to read the mode. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
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AM29F040
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are "don't-cares" when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 s to suspend the erase operation. When the device has entered the erase-suspended mode, DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Write Operation Status
Table 5.
Status Byte Programming in Embedded Algorithm Embedded Erase Algorithm In Progress Erase Erase Suspended Sector Suspended Non-Erase Suspended Sector Mode Byte-Programming in Embedded Algorithm Embedded Erase Algorithm
Write Operation Status
DQ7 DQ7 0 1 Data DQ7 0 DQ6 Toggle Toggle No Toggle Data Toggle Toggle DQ5 0 0 0 Data 1 1 DQ3 0 1 1 Data 0 1
Exceeded Time Limits
DQ7
Data Polling The AM29F040 device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device produces the compliment of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, reading the device produces the true data last written to DQ7. During the Embedded Erase Algorithm, reading the device produces a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, reading the device produces a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 3. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the AM29F040 data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the successive read attempts. The Data Polling feature is active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, or sector erase time-out (see Table 5).
AM29F040
11
See Figure 12 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit The AM29F040 also features the "Toggle Bit" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. See Figure 13 for the Toggle Bit timing specifications and diagrams.
If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The DQ5 failure condition may also appear if a user tries to program a "1" to a location previously programmed to "0". In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
DQ3
Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the command may not have been accepted. Refer to Table 5, Write Operation Status.
DQ5
Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 1. If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device.
Data Protection
The AM29F040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise.
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AM29F040
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, the AM29F040 locks out write cycles for VCC < VLKO (see DC Characteristics section for voltages). When VCC < VLKO, the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The AM29F040 ignores all writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent unintentional writes.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V IL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE or WE will not initiate a write cycle.
Sector Protect
Sectors of the AM29F040 may be hardware protected using programming equipment at the users factory. The protection circuitry will disable both program and erase functions for the protected sector(s). Requests to program or erase a protected sector will be ignored by the device.
AM29F040
13
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (see below)
Data Poll Device
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
17113E-7
Figure 1.
Embedded Programming Algorithm
14
AM29F040
EMBEDDED ALGORITHMS
Start Write Erase Command Sequence (see below) Data Polling or Toggle Bit Successfully Completed
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H Additional sector erase commands are optional Sector Address/30H
17113E-8
Figure 2. Embedded Erase Algorithm
AM29F040
15
Start
Read Byte (DQ0-DQ7) Addr = VA
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = XXXXH during chip erase
Yes
DQ7 = Data ? No No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Addr = VA
DQ7 = Data ? No Fail
Yes
Pass
17113E-9
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 3.
Data Polling Algorithm
16
AM29F040
Start
Read Byte (DQ0-DQ7) Addr = VA
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = XXXXH during chip erase
No
DQ6 = Data ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Addr = VA
DQ6 = Data ? Yes Fail
No
Pass
17113E-10
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1".
Figure 5.
Toggle Bit Algorithm
20 ns
20 ns +0.8 V -0.5 V -2.0 V 20 ns
17113E-11
Figure 6.
Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
17113E-12
Figure 7.
Maximum Positive Overshoot Waveform
AM29F040
17
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Ceramic Packages . . . . . . . . . . . . . . -65C to +150C Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground All pins except A9 (Note 1). . . . . . . . . -2.0 V to +7.0 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V A9 (Note 2). . . . . . . . . . . . . . . . . . . . -2.0 V to +13.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20ns. 2. Minimum DC input voltage on A9 pin is -0.5 V. During voltage transitions, A9 may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA). . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .-40C to +85C Extended (E) Devices Ambient Temperature (TA). . . . . . . . .-55C to +125C VCC Supply Voltages VCC for AM29F040-55. . . . . . . . . . +4.75 V to +5.25 V VCC for AM29F040 -70, -90, -120, -150 . . . . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
18
AM29F040
DC CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Note 1) VCC Active Program/Erase Current (Notes 2, 3) VCC Standby Current Input Low Level Input High Level Voltage for Autoselect and Sector Protect VCC = 5.25 V Output Low Voltage Output High Level Low VCC Lock-Out Voltage IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min 2.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, CE = VIH -0.5 2.0 10.5 Min Max 1.0 50 1.0 30 40 1.0 0.8 VCC + 0.5 12.5 0.45 Unit A A A mA mA mA V V V V V V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested.
AM29F040
19
DC CHARACTERISTICS (continued) CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH1 VOH2 VLKO Low VCC Lock-out Voltage Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Note 1) VCC Active Program/Erase Current (Notes 2, 3) VCC Standby Current (Note 4) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage VCC = 5.25 V IOL = 12.0 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min 0.85 VCC VCC -0.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.5 V -0.5 0.7 x VCC 10.5 20 30 1 Min Typ Max 1.0 50 1.0 30 40 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA A V V V V V V V
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested. 4. ICC3 = 20 A max at extended temperatures (> +85C).
20
AM29F040
AC CHARACTERISTICS Read Only Operations Characteristics
Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Standard tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 3) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 2, 3) Output Enable to Output High Z (Notes 2, 3) Output Hold Time from Addresses, CE or OE, Whichever Occurs First Min CE = VIL OE = VIL OE = VIL Test Setup Min Max Max Max Max -55 55 55 55 30 18 18 Speed Options (Note 1) -70 70 70 70 30 20 20 -90 90 90 90 35 20 20 -120 120 120 120 50 30 30 -150 150 150 150 55 35 35 Unit ns ns ns ns ns ns
tAXQX
tOH
0
0
0
0
0
ns
Notes: 1. Test Conditions (for -55):
Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level, input and output: 1.5 V and 1.5 V Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level, input and output: 0.8 V and 2.0 V
(for all others):
2. Output driver disable time. 3. Not 100% tested.
5.0 V IN3064 or Equivalent
2.7 k
Device Under Test CL
6.2 k
Diodes = IN3064 or Equivalent
17113E-13
Notes: For -55: CL = 30 pF including jig capacitance For all others: CL = 100 pF including jig capacitance
Figure 8.
Test Conditions
AM29F040
21
AC CHARACTERISTICS Write/Erase/Program Operations
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Standard tWC tAS tAH tDS tDH tOES Description Write Cycle Time (Note 2) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read (Note 2) Enable Toggle and Data Polling Hold (Note 2) Time Read Recover Time Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) Max Typ tWHWH3 tWHWH3 tVCS Chip Erase Operation (Note 1) Max VCC Setup Time (Note 2) Min 64 50 64 50 64 50 64 50 64 50 sec s 8 8 8 8 8 8 8 8 8 8 sec sec Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ tWHWH2 tWHWH2 -55 55 0 40 25 0 0 0 10 0 0 0 30 20 7 1 Speed Options -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 1 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 1 -120 120 0 50 50 0 0 0 10 0 0 0 50 20 7 1 -150 150 0 50 50 0 0 0 10 0 0 0 50 20 7 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s sec
tOEH
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1
tGHWL tCS tCH tWP tWPH tWHWH1
Notes: 1. This does not include the preprogramming time. 2. Not 100% tested.
22
AM29F040
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING WAVEFORMS
tRC Addresses tACC Addresses Stable
CE tOE OE (tDF)
WE (tCE) (tOH) High Z High Z
Outputs
Output Valid
17113E-14
Figure 9.
AC Waveforms for Read Operations
AM29F040
23
SWITCHING WAVEFORMS
Data Polling Addresses 5555H tWC CE tGHWL OE tWP WE tCS tWPH tDH Data tDS 5.0 V tCE
17113E-15
PA tAS tAH
PA tRC
tWHWH1
tOE PD DQ7 DOUT
tDF
A0H
tOH
Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 10. Program Operation Timings
tAH Addresses 5555H 2AAAH tAS CE tGHWL OE tWP WE tWPH tCS Data tDS VCC tVCS AAH 55H 80H AAH 55H 10H/30H tDH 5555H 5555H 2AAAH SA
17113E-16
Note: SA is the sector address for Sector Erase. Addresses = don't care for Chip Erase.
Figure 11.
AC Waveforms Chip/Sector Erase Operations
24
AM29F040
SWITCHING WAVEFORMS
CE tCH tOE OE tOEH WE tDF
tCE
*
DQ7 DQ7
tOH DQ7 = Valid Data High Z
tWHWH 1 or 2 DQ0 - DQ6 DQ0 - DQ6 = Invalid
DQ0 - DQ6 Valid Data
17113E-17
*DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 12.
AC Waveforms for Data Polling During Embedded Algorithm Operations
CE tOEH WE tOES OE * Data (DQ0-DQ7) tOH DQ6 = Toggle tOE
17113E-18
DQ6 = Toggle
DQ6 = Stop Toggling
DQ0-DQ7 Valid
*DQ6 stops toggling (The device has completed the Embedded operation.)
Figure 13.
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
AM29F040
25
AC CHARACTERISTICS Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Standard tWC tAS tAH tDS tDH tOES Description Write Cycle Time (Note 2) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read (Note 2) Enable Toggle and Data Polling Hold (Note 2) Time Read Recover Time Before Write WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) Max Typ tWHWH3 tWHWH3 tVCS Chip Erase Operation (Note 1) Max VCC Setup Time (Note 2) Min 64 30 64 50 64 50 64 50 64 50 sec s 8 8 8 8 8 8 8 8 8 8 sec sec Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ tWHWH2 tWHWH2 -55 55 0 40 25 0 0 0 10 0 0 0 30 20 7 1 Speed Options -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 1 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 1 -120 120 0 50 50 0 0 0 10 0 0 0 50 20 7 1 -150 150 0 50 50 0 0 0 10 0 0 0 50 20 7 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s sec
tOEH
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1
tGHEL tWS tWH tCP tCPH tWHWH1
Notes: 1. This does not include the preprogramming time. 2. Not 100% tested.
26
AM29F040
SWITCHING WAVEFORMS
Data Polling Addresses 5555H tWC WE tGHEL OE tCP CE tWS tCPH tDH Data tDS 5.0 V
17113E-19
PA tAS tAH
PA
tWHWH1
A0H
PD
DQ7
DOUT
Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 14.
Alternate CE Controlled Program Operation Timings
AM29F040
27
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Typ 1.0 (Note 1) 8 (Note 1) 7 (Note 1) 3.6 (Note 1) Max 8 64 300 (Note 2) 10.8 (Notes 2, 4) Unit sec sec s sec Comments Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Excludes system-level overhead (Note 3) Excludes system-level overhead (Note 3)
Notes: 1. 25C, 5 V VCC, 100,000 cycles. 2. Under worst case condition of 90C, 4.5 V VCC, 100,000 cycles. 3. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure. 4. The Embedded Algorithms allow for 1.8 ms byte program time. DQ5 = "1" only after a byte takes the theoretical maximum time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The majority of the bytes will program within one or two pulses (7 to 14 s). This is demonstrated by the Typical and Maximum Programming Times listed above.
LATCHUP CHARACTERISTICS
Min Input Voltage with respect to VSS on all I/O pins VCC Current -1.0 V -100 mA Max VCC + 1.0 V +100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
LCC PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
28
AM29F040
PLCC PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VPP = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
PDIP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VPP = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
AM29F040
29
PHYSICAL DIMENSIONS PD 032 32-Pin Plastic DIP (measured in inches)
1.640 1.680 32 17 .530 .580 16 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .008 .015
.600 .625
Pin 1 I.D.
SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060
16-038-SB_AG PD 032 DG75 2-28-95 ae
PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.447 .453
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
30
AM29F040
PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
0.17 0.27 7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TS 032 DA95 8-14-96 lv
AM29F040
31
PHYSICAL DIMENSIONS (continued) TSR032 32-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
0.17 0.27 7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TSR032 DA95 8-15-96 lv
32
AM29F040
DATA SHEET REVISION SUMMARY FOR AM29F040
Distinctive Characteristics Changed low power consumption specifications to typical values. Added "enhanced power management" bullet. General Description Fifth paragraph, changed sector erase time to 1.0 sec. Product Selector Guide Removed the -75 (70 ns, 5%) speed option. Ordering Information Added -55 speed option to the example part number. Removed the -75 speed option from the valid combinations. Added industrial and extended temperature ranges to -55 valid combinations. Added extended temperature to -70 valid combinations. Table 1--User Bus Operations Changed I/O write entry to "PD" and I/O read entry to "RD"; now matches Table 4. Corrected reference to tables in Note 2. Standby Mode Changed maximum CMOS standby mode current to 5 A. Autoselect Deleted fourth paragraph. Table 2--Autoselect Codes Changed table title. Table 3--Sector Addresses Changed table title. Sector Protection Reworded second paragraph, second sentence. Sector Unprotection Deleted after second sentence. Table 4--Command Definitions Added "X" to first cycle of first Read/Reset command. Changed fourth cycle in Byte Program row from "data" to "PD". Deleted Note 1. Rewrote Notes 2 and 6.
Sector Erase Changed time-out to 80 s. Deleted note. In second paragraph, deleted third sentence from end. In fourth paragraph, changed third sentence from end. User Note for Chip Erase and Sector Erase Commands Deleted section. Erase Suspend Deleted last sentence of fourth paragraph. Deleted fifth paragraph. Table 5--Write Operation Status Added overbars to DQ7. DQ7--Data Polling Fourth paragraph, added "Erase Suspend." DQ5--Exceeded Timing Limits Clarified first sentence in fifth paragraph. Absolute Maximum Ratings Corrected VSS in second sentence to V. Operating Ranges--VCC Supply Voltages Added -55 and -70 speed options. Deleted -75 speed option. DC Characteristics
TTL/NMOS Compatible: Changed ICC1, ICC2, and VID specifications. CMOS Compatible: Changed ICC1, ICC2, ICC3 and VID specifications, added typical values. Added Note 4.
AC Characteristics
Read Only Operations Characteristics: Removed -75 speed option. Changed tGLQV in -55 column to 30 ns. Combined Notes 1 and 2.
Figure 7--Test Conditions Changed first CL in note to -55. AC Characteristics
Write/Erase/Program Operations (also same table for Alternate CE Controlled Writes): Removed -75 speed option. Changed specifications on tWHWH1, tWHWH2, and tWHWH3.
Erase and Programming Performance Changed maximum specifications. Clarified note 5. Deleted Note 2.
Trademarks Copyright (c) 1996 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
AM29F040
33

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